1. Field of the Invention
The present invention relates to field-effect semiconductor devices and methods for making the same.
2. Description of the Related Art
In order to improve the characteristics of a field-effect transistor, it is important to reduce resistance of the gate electrode and to reduce parasitic resistance between the gate electrode and the source electrode and between the gate electrode and the drain electrode.
In GaN-based field-effect transistors, in most cases, gate electrodes, source electrodes, and drain electrodes are formed by patterning in sequence.
FIGS. 10A to 10F are sectional views which schematically show the steps in an example of a method for fabricating a GaN-based field-effect transistor.
First, as shown in FIG. 10A, a non-doped GaN layer 14 with a thickness of approximately 1 to 2 μm, a non-doped AlGaN spacer layer 15 with a thickness of 3 to 5 nm, a Si-doped AlGaN layer 16 with a thickness of 10 to 30 nm, and a non-doped AlGaN cap layer 17 with a thickness of 5 to 15 nm are formed in that order on an insulating substrate 12, such as a sapphire substrate or a SiC substrate, by a molecular beam epitaxy (MBE) process or a metal organic chemical vapor deposition (MOCVD) process.
As shown in FIG. 10B, an insulating film 2, such as a SiO2 insulating film, is formed, with a thickness of 20 to 30 nm, on the AlGaN cap layer 17 by a plasma-enhanced chemical vapor deposition (CVD) process or an electron-beam (EB) vapor deposition process. Next, although not shown in the drawing, a resist layer having a pattern with the dimensions of the device is formed, and the regions other than the operation layer is insulated by ion implantation, for example, using boron or nitrogen.
A gate electrode-forming resist layer 3 provided with an opening with a predetermined size is then placed on the SiO2 insulating film 2. A portion of the SiO2 insulating film 2 corresponding to the gate electrode-forming region is removed by CF4-based dry etching or HF-based wet etching.
Next, as shown in FIG. 10C, a gate electrode metal, for example, composed of Ni/Au, is deposited through the opening of the gate electrode-forming resist layer 3 to form a gate electrode 21. After the gate electrode metal is deposited, the resist layer 3 and the gate electrode metal which is deposited on the resist layer 3 and which is shown in phantom lines in FIG. 10C are removed by a lift-off process.
As shown in FIG. 10D, a resist layer 22 provided with openings for forming a source electrode and a drain electrode which are located at predetermined positions on both sides of the gate electrode 21 are formed by patterning. Portions of the SiO2 insulating film 2 corresponding to the regions for forming the source electrode and the drain electrode are removed again by dry etching or wet etching.
As shown in FIG. 10E, an ohmic metal, for example, Ti/Al, is deposited through the openings for forming the source electrode and the drain electrode, and a source electrode 8 and a drain electrode 9 are formed by a lift-off process.
Next, as shown in FIG. 10F, the ohmic metal (Ti/Al) constituting the source electrode 8 and the drain electrode 9 is alloyed, for example, using an infrared alloying furnace or a heat alloying furnace, and satisfactory ohmic contacts are obtained. An insulating film 23 composed of SiO2, SiN, or the like is then formed thereon, and the insulating film 23 formed on the electrodes is removed. A GaN-based field-effect transistor is thereby completed.
FIGS. 11A to 11C are sectional views which schematically show the steps in another example of a method for fabricating a GaN-based field-effect transistor.
First, as shown in FIG. 11A, an insulating film 2, such as a SiO2 insulating film, is formed, with a thickness of 20 to 30 nm, on an AlGaN cap layer 17 by a plasma-enhanced CVD process or an EB vapor deposition process. Next, although not shown in the drawing, a resist layer having a pattern with the dimensions of the device is formed, and the regions other than the operation layer is insulated by ion implantation, for example, using boron or nitrogen. A gate electrode-forming resist layer (first resist layer) 3 provided with an opening with a predetermined size is then formed on the SiO2 insulating film 2. A portion of the SiO2 insulating film 2 corresponding to the gate electrode-forming region is removed by CF4-based dry etching or HF-based wet etching.
A third resist layer 5 for forming a T-shaped gate electrode and a second resist layer 4 for preventing the mixture of the first resist layer 3 and the third resist layer 5 are placed on the gate electrode-forming resist layer 3, and an opening is formed again for the gate electrode-forming region. A portion of the SiO2 insulating film 2 corresponding to the T-shaped gate electrode-forming region is removed. A gate electrode metal, for example, composed of Ni/Au, is deposited through the opening, and a T-shaped gate electrode 6 is thereby formed. After the gate electrode metal is deposited, the resist layers 3 to 5 and the gate electrode metal deposited on the third resist layer 5 are removed by a lift-off process.
As shown in FIG. 11B, a resist layer 22 provided with openings for forming a source electrode and a drain electrode which are located at predetermined positions on both sides of the T-shaped gate electrode 6 are formed by patterning. Portions of the SiO2 insulating film 2 corresponding to the regions for forming the source electrode and the drain electrode are removed. As shown in FIG. 11C, an ohmic metal (Ti/Al) is deposited through the openings for forming the source electrode and the drain electrode to form a source electrode 8 and a drain electrode 9, and the resist layer 22 is removed by a lift-off process. After the source electrode 8 and the drain electrode 9 are formed, a GaN-based field-effect transistor is completed in the same manner as that described above.
However, in each of the methods for fabricating the GaN-based field-effect transistors described above, since the source electrode and the drain electrode are aligned by the exposure of the resist, it is impossible to reduce the distance between the gate electrode and the source electrode or the distance between the gate electrode and the drain electrode to a value below the alignment accuracy or the minimum dimensional precision of an exposure apparatus. Therefore, the resistance between the source and the gate and the resistance between the drain and the gate may be increased, resulting in a degradation in the device characteristics and also resulting in inferior uniformity and consistency among devices.